Errors can occur when information is transmitted between a transmitter and a receiver. Error correction codes, such as Low Density Parity Check (LDPC) codes, are often used to detect and correct such errors. LDPC codes are block codes based on a parity check matrix, H. See, for example, R. G. Gallager, “Low-Density Parity-Check Code,” IRE Trans. Inform. Theory, vol. IT-8, 21-28 (January 1962). LDPC codes are being proposed or suggested for use in a variety of transmission systems, such as satellite communications, wireless transmissions, fiber optics, and a variety of storage media, including hard disk drives, optical disks, and magnetic bands.
A given LDPC code is defined by a parity check matrix, H. A non-zero entry of the parity check matrix defines a parity check used to detect and correct errors in the received codeword. An LDPC parity check matrix is said to be sparse. In other words, there are a small number of non-zero entries in the matrix relative to the size of the matrix. If the parity check matrix, H, has dimension (n-k, n), a codeword is said to be n bits long with k information bits and n-k parity check bits. A parity check matrix for an (n, k) code has n columns and n-k rows.
Quasi-cyclic LDPC codes combine some of the advantages of random and structured code constructions. Encoding of random LDPC codes is typically an “order of n2” (O(n2)) operation. Quasi-cyclic LDPC codes combine good error rate performance with the opportunity for simplified encoding and decoding. As a result, quasi-cyclic LDPC codes have been proposed for the IEEE 802.16e standard.
LDPC decoders have traditionally been designed for a specific parity check matrix, H. Thus, the block length that the decoder processes and the rate of the code are fixed for the particular architecture. A need therefore exists for LDPC decoders that can support multiple code block lengths and code rates. A further need exists for LDPC decoders that can support a variable parity check matrix.